Part 1: An ESD Example

Signal Current Flow in a Layer Transition

Abstract: Printed circuit board, PCB, signal paths must often change layers in a board stackup. Under some conditions this can cause problems. An ESD example is used to illustrate the conditions where changing layers can cause problems.

Figure 1: Signal Paths Through a Via

Discussion:  Routing paths in a PCB often requires the paths to change layers to accomplish the layout. For a four layer PCB, this usually means changing from the top layer to the bottom layer of the board, the two middle layers being power and ground. A four layer board is especially problematical because generally the separation between the power and ground layers is relatively large, on the order of 30 to 40 mils, compared to boards with six or more layers.

Figure 1 shows the case of a signal path that changes from the top layer of a four layer board to the bottom layer.  While on the top and bottom layers, the signal current is matched by its image return current in the nearby ground or power plane. As the signal current changes layers from top to bottom an impairment that effects ESD performance can occur.

All signals form a loop, from source to load and back again to the source. It’s often the “back again” part of the path that gets us into trouble, as we shall see for this specific case. The signal’s returning current on the bottom of the bottom plane follows the signal to the top of the bottom plane, but it must pass through the interplane impedance, Z in Figure 1, to get to the bottom of the top plane from where it can follow the signal on to the top of the top plane.

Figure 2: Test Board with Paths on a Single Layer and Two Layers

One way to think of the impedance Z is to think of the the two planes as a two dimensional transmission line spreading out from the signal via. Bypass caps form low impedance “shorts” (although not all that good of a short at high enough frequencies where their inductance becomes important) and the edges of the board are generally unterminated “opens.” These and other features cause reflections that contribute to an interplane impedance that varies significantly with frequency and can reach several Ohms at some frequencies for a four layer board with plane spacings on the order of 30 mils. Murphy’s Law has it that one peak of this impedance will be at the third harmonic of your clock frequency!

To evaluate this effect, I constructed the test board shown in Figure 2. Each signal trace is about 30 cm long. The traces are composed of one conductor of 100 Ohm twisted pair telephone wire. When taped to the ground plane, it forms a 50 Ohm path. The board is a double copper clad board and the whole assembly simulates a four layer PWB. The two copper planes are spaced about 30 mils apart and are shorted together by the SMA connectors on the left and at the load resistors on the right, four locations. One path stays on one side while the other penetrates the board and runs for about 10 cm on the other side.

Figure 3

Test Board with Paths on a Single Layer and Two Layers

The board was subjected to a 3 kV ESD contact discharge from an ESD simulator to the end of a one meter cable fastened to the plane shown in Figure 2 near the middle of the right edge while the middle of the left edge was connected to ground to drain charge from the board. Figure 3 shows the resulting apparent signal at the SMA connector for the top path of Figure 2 that stayed on the same side of the board. That signal was only about 400 mV.

ESD Generated EMI to Path on One Layer

Figure 4 shows the apparent signal at the SMA connector of the lower path of Figure 2 that changed layers from the top to the bottom of the board and back. In this case, the peak signal at the SMA connector was over two volts peak and was oscillatory at the natural frequency of the assembly. This level would most certainly be a problem for most logic circuits. The increased noise in the lower path is due to the ESD causing a voltage drop across the interplane impedance, Z, at each transition from one side of the board to the other. This voltage shows up in the signal/return loop and therefore appears at the SMA connector.

Figure 4

ESD Generated EMI to Path on Two Layers

For cases where the interplane distance is much smaller than 30 mils, the interplane impedance will also generally be lower as well and the effect shown in Figure 4 will be smaller and less of a problem. The effect can also be minimized for a four layer board if critical signals transition from top to bottom of the board near existing (for low cost) bypass capacitors.

Summary: Transitioning between layers of a PWB can introduce significant impairment into a signal path. The larger the spacing between power and ground planes, the larger the effect. The example of a “four layer” PWB response to ESD shows one of the problems that can occur.

 

Part 2: An Emissions Example

Relative Emissions for Two Paths

Figure 5

Abstract: Printed circuit board, PCB, signal paths must often change layers in a board stackup. Under some conditions this can cause problems. An emissions example is used to illustrate the conditions where changing layers can cause problems.

Discussion:  Routing paths in a PCB often requires the paths to change layers to accomplish the layout. For a four layer PCB, this usually means changing from the top layer to the bottom layer of the board, the two middle layers being power and ground. A four layer board is especially problematical because generally the separation between the power and ground layers is relatively large, on the order of 30 to 40 mils, compared to boards with six or more layers.

Figure 5 depicts emissions from the board shown in Figure 2. The paths on the board are about 30 cm in length. One stays on the same side of the board while the other passes through to the other side for about 10 cm. The two metal planes are about 30 mils apart and are shorted together by the SMA connectors and at the 47 Ohm load resistors. The paths are made of one insulated conductor made from 24 gauge twisted pair telephone wire. Since the original cable had a differential impedance of 100 Ohms, one of the wires taped down to a copper plane will have a characteristic impedance of 50 Ohms with respect to the metal plane.

The data for Figure 1 was generated by exciting one path with the tracking generator of a spectrum analyzer and attaching an emissions measurement antenna to the input of the spectrum analyzer. The antenna had reasonable antenna factors up to about 3 GHz. Figure 6 shows the board sitting on a cardboard box in an EMC chamber. The coax on the left comes from the tracking generator and the one meter white wire on the right is just hanging off the box connected to one of the board planes by an alligator clip. It was included in case signal voltage on the planes might cause attached cables to radiate. The coaxial cable shield and the added wire form something of a dipole, albeit an asymmetric one.

Figure 6

Figure 5 was generated by overlaying emissions data from the two paths shown in Figure 2. The plots cover the frequency range from near DC up to 2.9 GHz. The absolute magnitude of the plots is not important. It depends on the output power of the tracking generator, but the comparison between the two plots is striking. The lower trace resulted from the path that stayed on one side of the board while the upper trace, showing pronounced peaks, resulted when the path that passed through the board was energized. Note that the first peak at 247 MHz is nearly 30 dB above the emissions at that frequency from the path that stayed on the same side of the board.

Figure 1 shows the signal currents in the wire and planes as the signal passes through the boards. A complex interplane impedance, Z, appears in the signal return path as it passes between the planes. The voltage generated across this impedance by the signal current as well as other effects contribute to the emissions shown in Figure 5.

For cases where the interplane distance is much smaller than 30 mils, the interplane impedance will also generally be lower as well and the effect shown in Figure 5 will be smaller and less of a problem. The effect can also be minimized for a four layer board if critical signals transition from the top layer to the bottom layer of the board near existing (for low cost) bypass capacitors.

Summary: Transitioning between layers of a PCB can introduce significant impairment into a signal path. The larger the spacing between power and ground planes, the larger the effect. The example of a “four layer” PCB emissions profile shows one of the problems that can occur.

 

Figure 7

Part 3: Interplane Voltage

Abstract: Four layer PCBs are used in a wide variety of applications. However, usually it is necessary for some signal paths to be routed on both the top and bottom signal layers to achieve required routing density. Using a model of a four layer PCB with ground and power planes, data is presented that shows routing a signal on both signal layers can cause significant signal voltage to be developed between the planes unless a simple design rule is observed.

Discussion: Figure 7 shows the test setup used to generate data, composed of an Agilent N9340B spectrum analyzer and a test board. The test board is copper clad on both sides and about 50 mils thick. A close-up of the bottom of the board is shown in Figure 2, before the BNC connector was added in the middle of the board. Two paths about 9 inches (~23 cm) in length run from SMA connectors to 51 Ohm load resistors. The paths are made from the individual insulated wires from 100 Ohm twisted pair telephone wire taped down to the underlying plane, thus forming an approximately 50 Ohm transmission line. One path stays on the bottom of the board while the other path runs about 1/3 of its length on the opposite side of the board.

Figure 8

The two planes are shorted together by the SMA connectors and at the load resistors. This simulates four bypass capacitors between the power and ground planes of a four layer PCB. Most four layer PCBs have more than four bypass capacitors, but I wanted to show a limiting case with only four. The results are worst case compared to most four layer PCBs. However, I have seen PCBs that needed additional bypass capacitors. In addition, passive four layer PCBs with no active components, such as a backplane, sometimes have few if any bypass capacitors.

Figure 8 shows a close-up of the top side of the test board. A BNC board mount connector has been soldered down to the top plane (and surrounded by copper tape to insure a good 360 degree contact from the plane to the connector). The center pin of the connector is soldered to the bottom plane so the signal at the BNC connector is the signal voltage between the planes. This connector is connected to the spectrum analyzer input while the tracking generator output of the analyzer is connected to one or the other of the BNC connectors that the signal paths on the bottom of the board are connected to (right side of Figure 3).

Figures 9 and 10 show the spectrum analyzer screens that resulted when the tracking generator was connected to the path that stayed on one side of the board and the path that was routed on both sides respectively. The tracking generator was set to its maximum level of 107 dBuV (0 dBm, about 224 mV). Note that the voltage between the planes is much larger for the path that was routed on both sides, tens of dB higher at most frequencies. At the first peak about 240 MHz, it is 45 to 50 dB higher.

Figure 9

Given that the applied signal was about 107 dBuV (into a 50 Ohm load) and the peak reading between the planes was about 93 dBuV at 240 MHz, the signal between the planes was only 14 dB less than the applied signal or about 1/5 of the applied signal. This implies the impedance between the planes must be several Ohms at least in the region of the center BNC connector at 240 MHz. Remember the planes are shorted together about 3 inches (1.2 cm) from the “vias” where the signal passed between the top and bottom of the board.

Figure 10

This is a limiting case compared with most four layer PCBs (only four “bypass caps”), but could represent a significant problem for passive backplanes and connecting boards which may have capacitors widely spaced if any at all. Some time ago I reviewed the layout of a passive board that connected SCSI signals between two parts of a system. The SCSI paths came in on the top layer of a four layer board and exited on the bottom layer on another connector. I had the person doing the layout add bypass capacitors in the field of vias of the SCSI signals as they passed from the top layer to the bottom layer to prevent the effect shown above.

Given the above data, one could propose a design rule for four layer boards where a critical signal (clock, reset, or similar) must pass from the top signal layer to the bottom signal layer of a four layer board. The via for this signal should be located near an existing or added bypass capacitor.

Summary: The use of a model of a four layer PCB shows that significant signal voltages can be developed between the planes of a four layer board under some circumstances. A resulting design rule could be to locate vias of important signals near bypass capacitors on four layer PCBs.

 

Part 4: Interplane Voltage Continued

Abstract: Four layer PCBs are used in a wide variety of applications. However, usually it is necessary for some signal paths to be routed on both the top and bottom signal layers to achieve required routing density. Using a model of a four layer PCB with ground and power planes, data is presented in the time domain that shows routing signals on both signal layers can cause significant signal voltage to be developed between the planes unless a simple design rule is observed.

Figure 11

Discussion: Figure 11 shows the test setup used to generate data, composed of a Fischer Custom Communications TG-EFT high voltage pulse generator, an Agilent Infinium 54845a scope, and a test board. The test board is copper clad on both sides and about 50 mils thick. A close-up of the bottom of the board is shown in Figure 2, before the BNC connector was added in the middle of the board. Two paths about 9 inches (~23 cm) in length run from SMA connectors to 51 Ohm load resistors. The paths are made from the individual insulated wires of 100 Ohm twisted pair telephone wire taped down to the underlying plane, thus forming approximately 50 Ohm transmission lines. One path stays on the bottom of the board while the other path runs about 1/3 of its length on the top side of the board (visible in Figure 1).

The two planes are shorted together by the SMA connectors and at the load resistors. This simulates four bypass capacitors between the power and ground planes of a four layer PCB. Most four layer PCBs have more than four bypass capacitors, but I wanted to show a limiting case with only four. The results are worst case compared to most four layer PCBs. However, I have seen PCBs that needed additional bypass capacitors. In addition, passive four layer PCBs with no active components, such as a backplane, sometimes have few if any bypass capacitors.

Figure 8 shows a close-up of the top side of the test board. A BNC board mount connector has been soldered down to the top plane (and surrounded by copper tape to insure a good 360 degree contact from the plane to the connector). The center pin of the connector is soldered to the bottom plane so the signal at the BNC connector is the signal voltage between the planes. This connector is connected to the scope input while the TG-EFT pulse generator output is connected to one or the other of the SMA connectors that the signal paths on the bottom of the board are connected to (right side of Figure 8). SMA to BNC adapters are used to interface the BNC cable to the scope.

The TG-EFT was set to produce 100 Volt pulses (with a rise time of 2 ns and a fall time of about 100 ns). This setting would produce a current pulse into the signal path on the board of about one Ampere since a 50 Ohm series termination was used on the output of the TG-EFT and the rest of the signal path is also 50 Ohms.

Figure 12

Figures 12 and 12 show the scope plots that resulted when the TG-EFT generator was connected to the path that stayed on one side of the board and the path that was routed on both sides respectively. For the path that stayed on the same side of the board, the plot in Figure 12 shows a peak amplitude of about 2 mV, a very small value. The peak amplitude of the plot in Figure 13 resulting from the path that passed between the top and bottom of the board is about 270 mV, a much larger signal. Note that the ringing frequency in Figure 13 is about 240 MHz, the same as the resonant frequency measured in the frequency domain on this board in the June 2010 Technical Tidbit. The main ringing frequency in Figure 12 is much slower and is of such a low amplitude, it may be present in Figure 13 as well but too small to be seen at the 100 mV/div vertical scale. That low frequency is not due to a resonance in the board as the frequency noted in Figure 13 is.

There are many scenarios where an Ampere or more of current can be dumped into the power-ground structure of a PCB. For example, a wide bus that changes from the top layer to the bottom layer of a backplane can generate substantial currents in the planes if the bits change all at once in the same direction. Modern busses can also be faster than the 2 ns rise time of the current used for this experiment, likely making the problem worse.

As a test for one of my clients, I once dumped almost 90 Amperes of current with a 5 ns rise time from the output of an EFT generator into the 3.3 Volt power plane of a PCB relative to the ground planes. No errors in the operation of the board were observed, a very good design and much better than our test board used here by two orders of magnitude or more.

Figure 13

This is a limiting case compared with most four layer PCBs (only four “bypass caps”), but the effect described could represent a significant problem for passive backplanes and connecting boards which may have capacitors widely spaced if any at all. Some time ago I reviewed the layout of a passive four layer board that connected SCSI signals between two parts of a system. The SCSI paths came in on the top layer and exited on the bottom layer to another connector. I had the person doing the layout add bypass capacitors in the field of vias of the SCSI signals as they passed from the top layer to the bottom layer to prevent the effect shown above.

Given the above data, one could propose a design rule for four layer boards where critical or noisy signals (bus, clock, reset, or similar) must pass from the top signal layer to the bottom signal layer of a four layer board: The vias for these signals should be located near an existing or added bypass capacitor.

Summary: The use of a four layer PCB model shows that significant signal voltages can be developed between the planes of a four layer board under some circumstances when signals are routed between the top and bottom layers. A resulting design rule could be to locate vias of noisy or important signals near bypass capacitors on four layer PCBs.

 

This is a guest post from Doug Smith, an electrical engineer who provides training and consulting services in general design, EMC, and transient immunity (such as ESD and EFT), and switching power supply noise. Learn more about Doug and his services by visiting his website, High Frequency Measurements.

 

 

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